1. Field of the Invention
The present invention relates to an internal memory and more particularly, to an internal memory of an application specific integrated circuit (ASIC) device.
2. Discussion of Related Art
As the application fields and designs for ASIC devices continue to increase, the ASIC chip becomes more complicated. Accordingly, the amount of memory required to support the variety of functions also increases significantly. Compared to the access time of a high-speed ASIC chip, an external memory such as a dynamic random access memory (DRAM) or a static random access memory (SRAM) has a considerably slow access time. Thus, depending upon the size and speed of the chip, there is a strong need for an internal memory.
When an internal memory is utilized in the chip, several conditions should be taken into consideration. First, the control signals in the internal memory should be designed and implemented to build a layout which meets the timing constraints such that the memory and chip can operate in a stable manner. Second, upon completing the fabrication of the ASIC chip, the chip should be tested to determine whether the memory operates in a normal manner. Generally, a core memory provided by a vendor is utilized as an internal memory and such memory is typically an asynchronous core memory in a high-speed ASIC.
For example, FIG. 1 shows a block diagram of an asynchronous two-port random access memory (TPRAM) in the related art, while FIG. 2 is a timing diagram which illustrates a read cycle of the two-port RAM in FIG. 1 and FIG. 3 is a timing diagram which illustrates a write cycle of the two-port RAM in FIG. 1. The conventional two-port RAM, as shown in FIG. 1, has a structure of an asynchronous two-port RAM, which is used as an internal memory. Referring to FIGS. 2 and 3, when a read enable signal REB and a write enable signal WEB are in an active state, a read address RA and a write address WA should not have a transition.
To satisfy the timing constraint, careful attention must be given to the place and route (PandR). In other words, when the chip is being operated by a high-speed clock, the timing margin for the control signals of the memory cannot be satisfied due to wire delay caused by the PandR. As a result, a set-up or hold violation occurs. Therefore, an effort of a back-end designer to change the floor-plan of the memory cell and to set an optimal routing is required. However, when the arrangement and layout of the chip is changed due to a change in the design and/or an addition of a new module, the arrangement and routing of core memory must be set again. Thus, one of the problems which arise is a difficulty in designing and re-using the memory core.
Also, a typical testing method used after the production of an internal memory is a Built in Self Test (BIST). The BIST requires a pseudo random pattern generator (PRPG) to generate a test pattern and access addresses, and a multiple input shift register (MISR) to compare the test results. To reduce the overhead in the flip-flop of the MISR and PRPG, a built-in logic block observe (BILBO) method which uses the flip-flops existing in the design may be employed. In the BILBO method, gates such as a few flip-flops and exclusive OR circuits for testing are added.
Furthermore, a fixed test pattern and an address incrementor are used as a comparable test method of the random test pattern. If the flip-flop existing in the design is used along with the address incrementor for the purpose of comparing the test results, the number of additional gates is similar to the number of gates used in the test using the BILBO. This method using the fixed test pattern can access all memory addresses but increases an error masking probability which is caused due to the fixed pattern.
Therefore, in the conventional asynchronous two-port RAM used as an internal memory in the ASIC, the timing margin for the control signals of the memory may not be satisfied when the chip is operated by a high-speed clock, resulting in a set-up or hold violation. Also, if the cell design is altered, there is a difficulty in re-using the memory. Finally, by using the random test pattern and a random address generator, there may be address areas where the test is not carried out, thereby increasing the error masking probability.
Accordingly, an object of the present invention is to solve at least the problems and disadvantages of the related art.
An object of the invention is to provide an internal memory in an ASIC device which is capable of allowing timing constraint to control signals in an asynchronous two-port RAM such that the ASIC device is stabilized.
Another object of the invention is to provide an internal memory in an ASIC device which easily allows re-use and re-design of the memory.
A further object of the invention is to provide a method for easily and accurately testing an internal memory in an ASIC device.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
To achieve the objects and in accordance with the purposes of the invention, as embodied and broadly described herein, an internal memory in an ASIC device, includes a two-port RAM in which read/write signals are processed by a single clock; first and second delays for delaying a write clock and a read clock to satisfy the timings of a write enable signal and a read enable signal of the two-port RAM; a first logic for inputting a synchronous write enable signal, a synchronous write address signal and a synchronous data in signal as a first input, and the write clock as a second input, said first logic inputting an output state based upon the input value to the two-port RAM; a second logic for logically ORing the synchronous write enable signal value input from the first logic and the output value from the first delay to output the OR-ed result to the write enable in the two-port RAM; a third logic for inputting a synchronous read enable signal, a synchronous read address signal and a synchronous data out signal as a first input, and the read clock as a second input, said third logic inputting an output state based upon the input value to the two-port RAM; and a fourth logic for logically ORing the synchronous read enable signal value input from the third logic and the output value from the second delay to output the OR-ed result to the read enable in the two-port RAM.
According to a second embodiment of the present invention, a method for testing an internal memory in an ASIC device, includes generating an address incrementor start signal in a state machine to an address incrementor, generating a test data select signal to an input pattern generator, and generating a compare enable signal to a test result comparator; sending a test address signal in the address incrementor inputting the address incrementor start signal to a memory tester and sending a test write data signal in the input pattern generator to the memory tester; inputting test read data in the memory tester in accordance with the test address signal in the address incrementor and the test write data in the input pattern generator, to the test result comparator; inputting and comparing the test result data of the memory tester and a shift in signal inputted from an arbitrary synchronous two-port RAM in the test result comparator; and shift-outputting the test result based upon the compared result.